The present invention relates to a microcontroller, more particularly to a microcontroller with reduced power consumption.
Referring to FIG. 1, a conventional microcontroller has a central processing unit (CPU) 1 and a read-only memory (ROM) 2. The data stored in the ROM 2 include a program that, when executed by the CPU 1, controls peripheral circuits (not visible) in the microcontroller, enabling the microcontroller to communicate with the outside world and perform various useful functions. Program instructions and other data read from the ROM 2 are passed to the CPU 1 through a data latch 3.
The ROM 2 has an enable terminal (CE) that receives a stop signal (STP) from the CPU 1. While the stop signal is at the low logic level, the ROM 2 is enabled and provides data (DAT) to the data latch 3 in response to address signals (ADR) received from the CPU 1. When the stop signal is at the high logic level, the ROM 2 conserves power by withholding data output. The data latch 3 also receives the stop signal. When the stop signal is at the low logic level, the data latch 3 operates transparently, passing the data (DAT) received from the ROM 2 immediately to the CPU 1. When the stop signal goes high, the data latch 3 holds and continues to output the last data (DAT) received while the stop signal was low. The state in which the stop signal is at the high logic level will be referred below to as a standby mode.
Normally, the CPU 1 holds the stop signal STP at the low logic level and executes instructions read sequentially from the ROM 2. From time to time, the CPU 1 issues a control command to a peripheral circuit, then sets the stop signal to the high logic level, stops program execution, and enters the standby mode to wait for the peripheral circuit to finish processing the command. Power is conserved because the ROM 2 also enters the standby mode.
When the peripheral circuit finishes processing the command, it sends the CPU 1 an interrupt signal (not shown), causing the CPU to resume program execution. Specifically, the CPU 1 reads the instruction held in the data latch 3 and sets the stop signal to the low logic level. The ROM 2 then resumes output of data (DAT) in response to further address signals received from the CPU 1.
Among the types of ROM employed in microcontrollers, one of the most advantageous is flash ROM, which is nonvolatile but can be electrically erased and reprogrammed. Flash ROM has a regular standby mode and a deep standby mode. Power consumption is greatly reduced in the deep standby mode, but recovery from that mode to the normal operating mode takes extra time. If the deep standby mode is employed in a conventional microcontroller, then when the CPU comes out of standby and attempts to read further instructions from the flash ROM, the flash ROM may be unstable and unable to provide correct output. To avoid consequent malfunctions, conventional microcontrollers employ the flash ROM's regular standby mode, which yields a comparatively modest reduction in power consumption.